This invention relates to duty cycle correction (DCC) methods and circuitry. Feed-forward duty cycle correction methods and circuits are used to recover or improve the quality of clock signals. Such methods and circuitry may be used at any stage in the clock path to improve the quality of the clock signal.
The duty cycle of a clock signal is the ratio of the pulse duration to the pulse period. A clock signal with 50% duty cycle is therefore in a HIGH logic state for half of the signal period, and in a LOW logic state for the other half of the signal period. Signals that are HIGH for more than half of the signal period have duty cycles above 50%, while signals that are LOW for more than half of the signal period have duty cycles below 50%.
High-speed circuits that use both the rising and falling edges of the clock signal for timing require clock signals that have 50% duty cycle. Circuits that rely on both clock edges include double-data rate (DDR) SDRAM circuits and half-rate clock and data recovery (CDR) circuits, for example. If the duty cycle of the clock signal in these circuits is not equal to 50%, the circuits may function improperly due to timing errors. Maintaining a 50% clock duty cycle in these circuits is therefore extremely important. Duty cycle correction circuits are commonly used to correct and adjust the duty cycle of clock signals in these high-speed circuits, to improve the quality of the clock signal and to ensure that a 50% duty cycle is maintained.
Two types of duty cycle correction circuits are commonly used, notably feedforward and feedback DCC circuits. The feedback DCC circuits typically have less jitter, better performance, and are less sensitive to noise than the feedforward types. However, they require more complicated circuitry and may introduce stability problems in the circuit. Feedforward DCC circuits can reduce the hardware complexity of the DCC circuitry, eliminate the feedback stability problems, and eliminate the training periods required by feedback correctors.
The performance of duty cycle correction methods and circuits may be measured in terms of the range of input signal duty cycles for which the circuit will function properly, in terms of how accurate or close to 50% the duty cycle of the output signal is, and in terms of the total current or power consumption of the duty cycle correction circuit. The present invention provides improved feed-forward duty cycle correction methods and circuits which function accurately with wide ranges of input signal duty cycles. In addition, the circuits presented function with reduced power consumption.